1. Field of the Invention
This invention relates generally to apparatus for the control of reading and writing of data to arrays of memory devices. In particular, this invention relates to apparatus for controlling the addressing patterns for controlling reading and writing of data to arrays of memory devices configured as a frame buffer for a video processing system receiving digital television signals.
2. Description of Related Art
Audio and video for broadcast television signals, including digital satellite and Cable television are currently encoded using MPEG-2. MPEG-2 is the designation for a group of audio and video coding standards agreed upon by MPEG (Motion Pictures Coding Experts Group), and published as ISO standard 13818. MPEG-2, with some modifications, is also the coding format used by standard commercial digital video disk (DVD) movies. The MPEG-2 encoded audio and video is modulated to create a transport stream for transmission either by a terrestrial radio frequency (RF) transmission, satellite RF transmission, cable television transmission, or storage on optical storage media such as the DVD. The transport stream is received, or in the case of the DVD, replayed, demodulated and decoded to recreate the audio and video signals for reproduction on a television or display monitor.
“A Cost Effective HDTV Decoder IC with Integrated System Controller, Down Converter, Graphics Engine and Display Processor,” Duardo, et al., IEEE Transactions on Consumer Electronics, August 1999, Volume: 45, Issue: 3, pp.: 879-883 describes a digital high definition television (HDTV) that supports MPEG-2 and other standards. Refer now to FIG. 1 for a discussion of a digital television video processor similar to that described in Durado, et al. A digital television processor 5 receives a digital television video stream 10 that has been received as a terrestrial RF transmission, satellite RF transmission, cable television transmission, or a data stream retrieved from a replayed DVD.
The demultiplexer 40 extracts video, audio, and data from the transport stream and sends it to the corresponding memory 20 via the memory controller 15. Data is stored in any of the memory 20 data queues. The demultiplexer 40 further creates the MPEG-2 transport layer packets that are reconciled into the packetized elementary streams. The packetized elementary streams are again buffered within the memory 20.
The stream processor 45 retrieves the MPEG-2 video elementary streams and converts the elementary streams to motion vectors and coefficients. The stream processor 45 further provides slice level error detection and concealment. The video decoder 50 receives the MPEG-2 compressed elementary streams. The video decoder 50 performs all required MPEG-2 functions such as motion compensation, inverse quantization, scaling, and etc. The optional graphics engine 55 provides all graphics functions and combines video with graphics.
The video format converter 60 retrieves the decompressed video data and converts the video data to generate the required raster formatting, timing, and filtering. The video format converter 60 generates the video signal as required by the display. In the case of a liquid crystal display (LCD) monitor this would be digital signals of the format required for the LCD. Alternately, in the instance of an analog display, the signals would be the red, green and blue analog signals necessary to drive the display.
The memory map is divided into buffers that retain compressed video, compressed audio, three frame stores for video decoding and display, graphics, data queues, and an address buffer. The memory controller 15 transfers data between the chip and the external memory 20 based on request order and priority. Each process has an assigned priority that determines when it is granted memory control relative to the other processes. Data received from memory 20 is stored in one of the line buffers 70a, 70b, 70c, and 70d until the requesting process can use it. Similarly, data to be stored in memory 20 is temporarily held line buffers 70a, 70b, 70c, and 70d until the direct memory access (DMA) interface 80 is allocated to the requesting process. The memory control function 85 manages the priority of the requesting processes, the locations, block sizes, and segmentation of the data within the memory 20.
The memory 20 maybe static random access memory (SRAM), RAMBUS dynamic random access memory (RDRAM), Synchronous dynamic random access memory (SDRAM), or other appropriately designed random access memory. The memory interface and bandwidth limitation is one of the most important design factors in a digital television system. Since all digital video processor systems require frame buffers, the memory 20 is commonly implemented as SDRAM. The memory controller 15 has become a major design consideration in digital video processor system. Due to the characteristics of SDRAM design, the access time is not a uniform parameter and thus causes a major design complexity in digital video processor systems. To resolve the non-uniform access time problem in SDRAM interface, the line buffers 70a, 70b, 70c, and 70d based on SRAM technology are required for the digital video processing system. The direct memory access controller 80 and line buffers 70a, 70b, 70c, and 70d have added major design complexity and die cost in most of the digital video processing integrated circuits.
The system processor 65 provides the interface provides the control, configuration, and detailed operational information useful for the video system configuration and debugging.
“Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM,” Hilgenstock, et al., Proceedings. Ninth Great Lakes Symposium on VLSI, 1999, pp.: 42-45 describes a programmable single-chip multiprocessor system for video coding applications. The multiprocessor system integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as a frame buffer and makes external memory for most applications not necessary. For fast access to local data segments also static RAM is integrated in each processing element.
U.S. Pat. No. 4,941,107 (Hasebe) teaches an image data processor for processing image data in a pipe line fashion. The image data processor includes an access controller for selectively generating addresses and control data in synchronism with a memory cycle in response to a start command, and for selectively and separately outputting the addresses onto address buses and the control data onto control buses. Memory planes selectively receive one address from one of the address buses, control data from one of the control buses, and selectively output data stored at the received address onto one of the data buses in synchronism with the memory cycle. The image data processor selectively executes a predetermined processing operation on data received from the memory planes, and selectively stores a result of the processing operation to the memory planes.
U.S. Pat. No. 6,424,347 (Kwon) illustrates an interface control for a frame buffer. The interface control includes a byte swapping/sampling controller connected between the PCI host bus and a FIFO (First In First Out) for performing a data conversion between a big Endian data and a little Endian data or a data conversion between a system data and a user data. A byte conversion/view selection controller is connected between the FIFO and the SRAM for converting a pixel data stored in the FIFO from a 8 bit-1 byte data to a 9 bit-1 byte data in accordance with a view selected or converting a pixel data stored in the SRAM from a 9 bit-1 byte data into a 8 bit-1 byte in accordance with a view selected. A Rambus Access Controller controls transmission of pixel data between the SRAM and a RAM bus DRAM, and a display controller for receiving a pixel data outputted from the RAM bus DRAM through the Rambus Access Controller and outputting to a RAM D/A converter through the display bus, for thereby concurrently performing a pixel data conversion between a big Endian and a little Endian and a pixel data conversion for a 8 bit-1 byte and 9 bit-1 byte in a 8 bit-1 byte PCI host bus and a 9 bit-1 byte RAM bus DRAM each using a system memory having different byte definition and bus configuration.
U.S. Pat. No. 5,291,275 (Lumelsky) describes a triple field buffer for television image storage and visualization on raster graphics display. The image conversion apparatus provides for storing in a first memory a first image field and for storing in a second memory a second image field. The first and the second memories are read to retrieve the first and second image fields and the first and second image fields are simultaneously displayed on a display screen as a single image frame. During the reading of the first and second memories, a third image field is stored in a third memory. The first, second and third memories are structured as a frame buffer having a 3×3 memory block organization. For image fields numbered 1, 2, 3, 4, 5, . . . , n, the system reads the image fields two at a time in accordance with a predetermined sequence given by: 1 and 2, 2 and 3, 3 and 4, 4 and 5, (n−1) and n, n and (n+1). A high resolution frame length is selected to be longer than or shorter than a television field period. The phase difference between the two is measured and circuitry alters the predetermined read-out sequence to ensure that a field memory to be read will not also be required for simultaneously storing a next television field.
U.S. Pat. No. 6,263,023 (Ngai) teaches a high definition television decoder. The high definition television video decoder decodes data at a high rate using multiple slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices of the HDTV signals are allocated to decoders optimally in response to busy signals providing improved performance.